Quatech MPAP-100 User Manual download pdf (Page 37)

10.2.2 Receive FIFO

The receive FIFO can service the receiver of either channel A or channel B of the SCC.

If RXSRC (bit 1) of the Configuration Register (see page 41) is logic 1, the receive FIFO will

service SCC channel B. If RXSRC is logic 0, the receive FIFO will service SCC channel A.

If the FIFOs are enabled, an I/O read from either SCC Data Port (channel A or channel B)

will read a byte from the receive FIFO. If the FIFOs are not enabled, an I/O read from the SCC

Data Port will instead read directly from the internal receive buffer of the specified channel of the

SCC.

10.3 SCC configuration for FIFO operation

The interface between the SCC and the external FIFOs uses the SCC's DMA request

functions. The SCC must therefore be configured for DMA operation in order to use the external

FIFOs. In order to properly configure the SCC, certain bits in various SCC registers need to be

set in a specific manner, as shown on the following pages.

Because the data transfer between the FIFOs and the SCC is controlled entirely by

hardware, per-character transmit and receive interrupts should be disabled. Interrupts on transmit

underruns and/or special receive conditions should usually be enabled so that end-of-frame

conditions can be detected.

IMPORTANT

The DMA operation described in this section is

between the SCC and the external FIFOs, and is

handled entirely by the MPAP-100 hardware.

DMA is not supported between the MPAP-100 and

the host computer due to the lack of DMA facilities

on the PCMCIA bus.

The MPAP-100 is a single-channel device. Accordingly, most applications will use SCC

channel A for both transmit and receive operations. It is possible, however, to use a limited

portion of SCC channel B for receive operations (see page 29). The channel used for receive will

determine how the SCC must be configured.

Do not enable the FIFOs until the SCC has been properly configured for DMA

operation!

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Quatech MPAP-100 User Manual Page 37