Quatech MPAP-100 User Manual download pdf (Page 48)

13 Interrupt Status Register

The Interrupt Status Register is used to determine the cause of an interrupt generated by

the MPAP-100. The address of this register is Base+8. Table 11 details the bit definitions of the

INTSCC for any of the statuses indicated by this register to occur. This register can be

ignored if the external FIFOs are not being used.

SCCTX_FIFORX_FIFORX_PAT0000

Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7

Table 11 --- Interrupt Status Register - Read Only/Write Clear

Bits 7-4: Reserved, always 0.

Bit 3: RX_PAT --- Receive Pattern Interrupt: The

receive pattern interrupt occurs when the character set in the Receive Pattern

Character Register is detected 'n' consecutive times in the received data stream,

where 'n' is the value set in the Receive Pattern Count Register. This bit is set

(logic 1) to indicate the interrupt. It remains set until cleared by writing a '1' to

this bit.

Bit 2: RX_FIFO --- Receive FIFO Interrupt:

The receive FIFO interrupt occurs when the number of bytes held in the external

receive FIFO rises above the half-full mark, or when a receive FIFO timeout

occurs. This bit is set (logic 1) to indicate the interrupt. It remains set until

cleared by writing a '1' to this bit.

Bit 1: TX_FIFO --- Transmit FIFO Interrupt: The

transmit FIFO interrupt occurs when the number of bytes held in the external

transmit FIFO falls below the half-full mark. This bit is set (logic 1) to indicate

the interrupt. It remains set until cleared by writing a '1' to this bit.

Bit 0: SCC --- SCC Interrupt:

If this bit is set (logic 1), the SCC has generated an interrupt. Software should

clear the interrupt condition by performing appropriate service on the SCC. This

bit is not latched.

1 2 ... 43 44 45 46 47 48 49 50 51 52 53 ... 63 64

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Quatech MPAP-100 User Manual Page 48