Quatech MPAP-100 User Manual download pdf (Page 50)

15 FIFO Control Register

The FIFO Control Register is used to control the external data FIFOs. The address of this

ignored if the external FIFOs are not being used.

TX_RESET000RX_RESETEN_TOEN_PAT0

Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7

Table 13 --- FIFO Control Register - Read/Write

Bit 7: Reserved, always 0.

Bit 6: EN_PAT --- Enable Receive Pattern Detection: Set this

bit (logic 1), to enable the receive pattern detection circuitry. Clear this bit (logic

0), to disable pattern detection. See page 37 for details on the receive pattern

detection feature.

Bit 5: EN_TO --- Enable Receive Timeout:

Set this bit (logic 1), to enable the external receive FIFO timeout. Clear this bit

(logic 0), to disable the receive FIFO timeout. See page 38 for details on the

receive FIFO timeout feature.

Bit 4: RX_RESET --- Reset Receive FIFO:

Set (logic 1), then clear (logic 0) this bit to reset the external receive FIFO. The

FIFO can be reset only when it is disabled.

Bits 3-1: Reserved, always 0.

Bit 0: TX_RESET --- Reset Transmit FIFO:

Set (logic 1), then clear (logic 0) this bit to reset the external transmit FIFO. The

FIFO can be reset only when it is disabled.

1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 63 64

No comments

Quatech MPAP-100 User Manual Page 50