Quatech MPAP-100 User Manual download pdf (Page 55)

N/C

RxCLK (DTE)

SYNCA

N/C

DGND

DSR

CTS

RTS

RxD

TxD

CGND

TM (OUTPUT)

TxCLK (DTE)

N/C

RLBK (OUTPUT)

DTR

N/C

LLBK (OUTPUT)

RxCLK (DCE)

N/C

TxCLK (DCE)

RING

Figure 2 --- MPAP-100 Output Connector

The testing signals the DTE can generate are Local Loopback (LL) and Remote Loopback

(RL). These signals are asserted with certain bits in the Communications Register. When a Test

Mode (TM) condition is received from the DCE, an interrupt can optionally be generated.

19.1 SYNCA (pin 10)

If EXTSYNC (bit 6) in the Communications Register is set to a logic 1, the SYNCA

signal from the connector is used to drive the active-low SYNC input of SCC channel A. The

signal is inverted by the RS-232 receiver, so a positive voltage on pin 10 will assert SYNCA.

The SCC must be specifically programmed to recognize external synchronization.

19.2 RING (pin 22)

If Card and Socket Services has set the SIGCHG bit in the PCMCIA Configuration Status

signal is inverted by the RS-232 receiver, so a positive voltage on pin 22 will assert STSCHG.

Table 17 shows the pin configuration of the MPAP-100 DTE connector. The definitions

of the interchange circuits according to the RS-232-D standard can be found starting on page 52.

SCC Pin or Register Bit

RS-232-D

Circuit

Signal

From

DTE

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 63 64

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Quatech MPAP-100 User Manual Page 55