Quatech MPAP-100 User Manual download pdf (Page 6)

1 Introduction

The Quatech MPAP-100 is a PCMCIA Type II (5 mm) card and is PCMCIA PC Card

Standard Specification 2.1 compliant. It provides a single-channel RS-232 synchronous

communication port. The base address and IRQ are configured through the PCMCIA hardware

and software using utility programs provided by Quatech. There are no switches or jumpers to

set.

The MPAP-100 uses a Zilog 85230-compatible Serial Communications Controller

(SCC). The SCC can support asynchronous formats, byte-oriented synchronous protocols such

as IBM Bisync, and bit-oriented synchronous protocols such as HDLC and SDLC. The SCC also

offers internal functions such as on-chip baud

rate generators, and digital phase-lock loop (DPLL) for recovering data clocking from received

data streams.

Because the PCMCIA 2.1 standard does not include a direct memory access (DMA)

interface, the MPAP-100 supports only interrupt-driven communications. To compensate for the

lack of DMA, the MPAP-100 is equipped with 1024-byte FIFOs for transmit and receive data.

The FIFOs provide for high data throughput with very low interrupt overhead.

1.1 System Requirements

 16 bytes of contiguous I/O address space

 one hardware interrupt (IRQ)

 One available PCMCIA Type II socket

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Quatech MPAP-100 User Manual Page 6