Quatech MPAP-100 User Manual download pdf (Page 40)

10.4 FIFO status and control

Several registers are used to control the FIFOs and monitor their status. These registers

are detailed in other chapters of this manual.

10.4.1 Interrupt status

Three interrupt statuses, listed in Table 8, can be generated by four events related to FIFO

activity. In each case, a latched bit in the Interrupt Status Register is set to a logic 1 (see page

43). These bits are write-clear, meaning that software must write a 1 to a bit in order to clear it.

IMPORTANT

FIFO-related interrupts will occur only when the

MPAP-100 interrupt source is set to INTSCC. See Table

10 on page 41 for details.

Software can read data

from the receive FIFO as

desired.

RX_PAT

(bit 3)

Special receive pattern

detected

Software can read bytes

from the receive FIFO until

the FIFO is empty.

Receive data timeout with

non-empty FIFO

Software can read at least

512 bytes from the receive

FIFO.

RX_FIFO

(bit 2)

Receive FIFO filled past

the half-full mark

Software can write at least

512 bytes to the transmit

FIFO.

TX_FIFO

(bit 1)

Transmit FIFO drained

past the half-full mark

Comment

Interrupt Status

Event

Table 8 --- FIFO-related interrupt statuses

IMPORTANT

Software can differentiate between the two types of

RX_FIFO interrupts by examining the RXH bit in the

FIFO Status Register. If RXH is clear (logic 0), the

interrupt occurred because of a timeout.

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 63 64

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Quatech MPAP-100 User Manual Page 40

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